Heretofore, lateral insulated gate transistors have been fabricated on semiconductor substrates which are either lightly doped, or moderately doped but not heavily doped. Various forms of vertical insulated gate transistors are disclosed in commonly-assigned U.S. Patent application Ser. No. 212,181 filed Dec. 2, 1980 by B. J. Baliga and entitled "Gate Enchanced Rectifier", now abandoned in favor of continuation application Ser. No. 483,009 incorporated by reference herein. As described in detail in the above application, an insulated gate transistor is a semiconductor device having an insulated gate for controlling the flow of carriers in an induced channel between the primary terminals of the device such as the anode and cathode terminals. The type of device which is referred to herein as an "insulated gate transistor" now has the official JEDEC designation "insulated gate bipolar transistor" or "IGBT." The gate establishes a conduction channel, the maximum capacity of which limits the maximum carrier current that can be carried by the device. The basic insulated gate transistor has both forward and reverse blocking capability. Current conduction in the forward direction can be controlled by the insulated gate which establishes the channel. The voltage applied to the insulated gate establishes the current capacity of the channel, and hence, the maximum carrier current that can be carried by the device. The insulated gate transistor is a bilateral device and employs conduction by both holes and electrons which contribute to the total current flow in the device. The channel is located adjacent one surface of the device and controllably supplies a flow of current of one type charge carrier to the drift region of the device while a heavily doped region located on the opposite surface of the device, supplies charge carriers of the opposite conductivity to the drift region. The carriers recombine in the drift region establishing a current flow across the device in response to appropriately applied bias potentials.
Heretofore circuit applications for lateral implementations of this device have been somewhat limited in view of the predisposition of this lateral type device to latch into uncontrolled current conduction. Further, the level of current conduction achieved before the occurrence of latch-up by these prior lateral embodiments was insufficient.